VHDL for logic synthesis / (Record no. 11123)
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| 003 - CONTROL NUMBER IDENTIFIER | |
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| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20171224113644.0 |
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| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
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| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 110609s2011 enka ob 001 0 eng d |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER | |
| Canceled/invalid LC control number | 2010045678 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | DG1 |
| Language of cataloging | eng |
| Description conventions | pn |
| Transcribing agency | DG1 |
| Modifying agency | BTCTA |
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| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781119995852 |
| Qualifying information | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 111999585X |
| Qualifying information | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780470977927 |
| Qualifying information | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 0470977922 |
| Qualifying information | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Cancelled/invalid ISBN | 9780470688472 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Cancelled/invalid ISBN | 0470688475 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Cancelled/invalid ISBN | 9780470977972 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Cancelled/invalid ISBN | 0470977973 |
| 024 8# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 9786613373892 |
| 029 1# - (OCLC) | |
| OCLC library identifier | AU@ |
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| OCLC library identifier | DKDLA |
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| 029 1# - (OCLC) | |
| OCLC library identifier | HEBIS |
| System control number | 299832473 |
| 029 1# - (OCLC) | |
| OCLC library identifier | NZ1 |
| System control number | 13876206 |
| 029 1# - (OCLC) | |
| OCLC library identifier | DEBBG |
| System control number | BV043393202 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)729726229 |
| Canceled/invalid control number | (OCoLC)704380182 |
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| -- | (OCoLC)765135622 |
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| -- | (OCoLC)839224154 |
| -- | (OCoLC)961512165 |
| -- | (OCoLC)962669173 |
| 037 ## - SOURCE OF ACQUISITION | |
| Stock number | 10.1002/9781119995852 |
| Source of stock number/acquisition | Wiley InterScience |
| Note | http://www3.interscience.wiley.com |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7885.7 |
| Item number | .R87 2011 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM |
| Subject category code subdivision | 036000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC |
| Subject category code subdivision | 008030 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC |
| Subject category code subdivision | 008050 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39/5 |
| Edition number | 22 |
| 049 ## - LOCAL HOLDINGS (OCLC) | |
| Holding library | MAIN |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Rushton, Andrew, |
| Dates associated with a name | 1962- |
| 245 10 - TITLE STATEMENT | |
| Title | VHDL for logic synthesis / |
| Statement of responsibility, etc | Andrew Rushton. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 3rd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Chichester, West Sussex, U.K. : |
| Name of publisher, distributor, etc | Wiley, |
| Date of publication, distribution, etc | 2011. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (xvi, 466 pages) : |
| Other physical details | illustrations |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Front Matter -- Introduction -- Register-Transfer Level Design -- Combinational Logic -- Basic Types -- Operators -- Synthesis Types -- Std_Logic_Arith -- Sequential VHDL -- Registers -- Hierarchy -- Subprograms -- Special Structures -- Test Benches -- Libraries -- Case Study -- Appendix A: Package Listings -- Appendix B: Syntax Reference -- References -- Index. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc | Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | "Macrocycles: Construction, Chemistry and Nanotechnology Applications is an essential introduction this important class of molecules and describes how to synthesise them, their chemistry, how they can be used as nanotechnology building blocks, and their applications"-- |
| -- | Provided by publisher. |
| 588 0# - | |
| -- | Print version record. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | VHDL (Computer hardware description language) |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic design |
| General subdivision | Data processing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-aided design. |
| 650 04 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | VHDL (Bilgisayar donanımı tanımlama dili) |
| 650 04 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Mantık tasarımı |
| General subdivision | Bilgi işlem. |
| 650 04 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Bilgisayar destekli tasarım. |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | VHDL (Computer hardware description language) |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic design |
| General subdivision | Data processing. |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-aided design. |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | COMPUTERS |
| General subdivision | Computer Engineering. |
| Source of heading or term | bisacsh |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | COMPUTERS |
| General subdivision | Logic Design. |
| Source of heading or term | bisacsh |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | TECHNOLOGY & ENGINEERING |
| General subdivision | Electronics |
| -- | Circuits |
| -- | Logic. |
| Source of heading or term | bisacsh |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | TECHNOLOGY & ENGINEERING |
| General subdivision | Electronics |
| -- | Circuits |
| -- | VLSI & ULSI. |
| Source of heading or term | bisacsh |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-aided design. |
| Source of heading or term | fast |
| -- | (OCoLC)fst00872701 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic design |
| General subdivision | Data processing. |
| Source of heading or term | fast |
| -- | (OCoLC)fst01002048 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | VHDL (Computer hardware description language) |
| Source of heading or term | fast |
| -- | (OCoLC)fst01163476 |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | VHDL (Computer hardware description language) |
| Source of heading or term | local |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic design / Data processing. |
| Source of heading or term | local |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer-aided design. |
| Source of heading or term | local |
| 655 #4 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 655 #4 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Llibres electrònics. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Print version: |
| Main entry heading | Rushton, Andrew. |
| Title | VHDL for logic synthesis. |
| Edition | 3rd ed. |
| Place, publisher, and date of publication | Chichester, West Sussex, U.K. : Wiley, 2011 |
| International Standard Book Number | 9780470688472 |
| Record control number | (DLC) 2010045678 |
| -- | (OCoLC)664324141 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="http://onlinelibrary.wiley.com/book/10.1002/9781119995852">http://onlinelibrary.wiley.com/book/10.1002/9781119995852</a> |
| Public note | Wiley Online Library |
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